archives/ruby3.2: new aport

archives/ruby3.2/fix-riscv64-build.patch

@@ -0,0 +1,38 @@
+Patch-Source: https://lists.openembedded.org/g/openembedded-core/message/161168
+partially extracted to actually apply onto a release tarball
+
+---
+From dfb22e4d6662bf72879eda806eaa78c7b52b519e Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Tue, 25 Jan 2022 20:29:14 -0800
+Subject: [PATCH] vm_dump.c: Define REG_S1 and REG_S2 for musl/riscv
+
+These defines are missing in musl, there is a possible
+patch to add them to musl, but we need a full list of
+these names for mcontext that can be added once for all
+
+Upstream-Status: Inappropriate [musl bug]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ vm_dump.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/vm_dump.c b/vm_dump.c
+index a98f5aa..957b785 100644
+--- a/vm_dump.c
++++ b/vm_dump.c
+@@ -39,6 +39,11 @@
+ 
+ #define MAX_POSBUF 128
+ 
++#if defined(__riscv) && !defined(__GLIBC__)
++# define REG_S1 9
++# define REG_S2 18
++#endif
++
+ #define VM_CFP_CNT(ec, cfp) \
+   ((rb_control_frame_t *)((ec)->vm_stack + (ec)->vm_stack_size) - \
+    (rb_control_frame_t *)(cfp))
+-- 
+2.35.0
+